1. Technical Field
The invention relates generally to semiconductor fabrication, and more particularly, to test structures and a method of detecting defects using voltage contrast inspection.
2. Background Art
In-line voltage contrast (VC) inspection is a powerful technique for detecting and isolating yield limiting defects in the semiconductor fabricating industry. In-line VC inspection includes scanning the wafer surface in which test structures exist with a scanning electron microscope (SEM). As the inspection proceeds, the SEM induces charge on all electrically floating elements whereas any grounded elements remain at zero potential. This potential difference is visible to the SEM. In particular, for electron landing energies less than the second crossover of the secondary electron yield curve (approximately 1.5 keV for tungsten (W) and copper (Cu)), grounded elements appear bright whereas floating elements appear dark.
Test structures exploiting this phenomenon can be created for many yield limiting defects including metal, gate and active region shorts and opens, and via and contact opens. For example, FIGS. 1A-B, show a short (FIG. 1B) indicated by a normally floating (dark) element becoming bright, and an open (FIG. 1A) indicated when a normally bright element becomes dark. As shown, even if the defect causing the electrical failure is buried or extremely small, its existence is indicated by a change in the VC signal of the entire element. In addition, the exact location of an open is indicated by a change in the VC signal of the structure after the break.
In addition to timely detection of yield limiting defects, this technique has several other major advantages. First, the location of a defect is flagged by the VC signal. Even if the defect causing the short is buried or extremely small, the VC signal appears on the entire element. Second, large areas can be inspected providing a large volume of data.
Transistor level defects such as dislocations and silicide pipes causing source to drain shorts is a problem in state of the art microelectronic fabrication due to the small scale of today's state of the art transistors. New methods to reduce these defects are required. Voltage contrast inspection may be applied to this problem. For a p-type field effect transistor (PFET), a simple test structure may be created in which the source is grounded and the state (grounded or floating) of the drain is sensed. If the drain appears bright in the SEM, this indicates a short through the transistor. Unfortunately, a similar device for an n-type field effect transistor (NFET) does not work because under electron extraction conditions (i.e., where a positive charge is induced on the surface), the gate of the device charges up just like any other exposed floating structure. Once the gate sufficiently charges to reach the turn-on voltage, the NFET turns on. In this case, the drain appears grounded (bright) for both good and defective transistors. This structure could be inspected using electron retarding conditions (i.e., where a negative charge is induced on the surface), but extraction conditions provide much better resolution than electron retarding conditions and are not only preferable but possibly necessary for future technologies. Another drawback of operating in electron retarding conditions is that the PFETs would now turn on. Therefore, NFET and PFET structures could not be inspected in the same scan.
One approach to providing a solution to this problem is to inspect for source-to-drain shorts after contact formation of the first metal level. In this case, the test structure may be designed so that no exposed conductor would make contact to the gate so that the gate would not charge up and turn on. One drawback to this approach is that substantial additional processing is required causing a substantial time penalty in the learning cycle and substantial additional investigative work to identify the failure once detected. In another approach, failures are isolated using an electrical test and then the cause of the failures are investigated and identified using standard failure analysis techniques. This approach, however, requires substantially more time for additional processing, test and then failure analysis. Also failures are isolated one at a time rather than in large numbers as with large area VC inspection.
In view of the foregoing there is a need in the art for a solution to the problems of the related art.